The present invention concerns the design and manufacture of very large scale integrated (VLSI) circuits and pertains particularly to improved routing within a datapath block within an integrated circuits.
When designing integrated circuits, logic blocks are located on the integrated circuit. Conductive lines are routed between and within logic blocks. Datapath blocks, such as register stacks, pose some challenging electrical and routing issues for designers. These regular structures often have signals and/or busses which span long distances. The need for density often dictates that signal-to-signal spacing be minimal. Typically, datapath blocks have a series of tracks which are used for routing data signals. These tracks are often designed to have a minimal width with minimal space between the tracks. While this results in conserving the space on the integrated circuit utilized to implement datapath blocks, there is also a certain amount of capacitive coupling which can occur between the lines. For tracks where the width of tracks and the spacing between tracks are each in the range of 1.2 microns, the capacitive coupling between a metal line in one track and metal lines in adjoining tracks can be as high as 60%. The resulting coupling noise (also referred to as crosstalk) can result in corruption of data stored within registers.